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Chapter 1: About This MegaCore Function
1–5
IP Core Verification
IP Core Verification
Before releasing a version of the RapidIO IP core, Altera runs comprehensive
regression tests in the current version of the Quartus ? II software. These tests use the
MegaWizard ? Plug-In Manager and the Qsys system integration tool to create the
instance files. These files are tested in simulation and hardware to confirm
functionality.
Altera also performs interoperability testing to verify the performance of the IP core
and to ensure compatibility with ASSP devices.
The RapidIO IP core v9.0 successfully passed RIOLAB’s Device Interoperability
Level-3 (DIL-3) testing in 2009.
Simulation Testing
Altera verifies the RapidIO IP core using the following industry-standard simulators:
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ModelSim ? simulator
VCS in combination with the Synopsys Native Testbench (NTB)
The test suite contains testbenches that use the RapidIO bus functional model (BFM)
from the RapidIO Trade Association to verify the functionality of the IP core.
The regression suite tests various functions, including the following functionality:
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Link initialization
Packet format
Packet priority
Error handling
Throughput
Flow control
Constrained random techniques generate appropriate stimulus for the functional
verification of the IP core. Functional coverage metrics measure the quality of the
random stimulus, and ensure that all important features are verified.
Hardware Testing
Altera tests and verifies the RapidIO IP core in hardware for different platforms and
environments.
The hardware tests cover serial 1x, 2x, and 4x variations running at 1.25, 2.5, 3.125,
and 5.0 Gbaud, and processing the following traffic types:
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NREAD s of various size payloads—4 bytes to 256 bytes
NWRITE s of various size payloads—4 bytes to 256 bytes
NWRITE_R s of a few different size packets
SWRITE s
Port-writes
DOORBELL messages
May 2013
Altera Corporation
RapidIO MegaCore Function
User Guide
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